 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 11211hkim 20100907-s00002 no.a1835-1/24 ver.1.01 LC87F1L16A overview the LC87F1L16A is an 8-bit microcom puter that, centered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 16k-byte flash rom (onboard programmable), 2048-byte ram, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer (may be divided into 8-bit timers or pwms), four 8-b it timers with a pres caler, a base timer serving as a time-of- day clock, a synchronous sio interface with automatic data transfer capabilities, an as ynchronous/synchronous sio interface, a uart interface (full duplex), 2 channels of fu ll-speed usb interface (host cont rol function), a 12-bit 12- channel ad converter, 2 channels of 12-bit pwm, a system clock frequency divider, and a 39-source 10-vector interrupt feature. features ? flash rom ? capable of on-board programming with a wide range of supply voltages: 3.0 to 5.5v ? block-erasable in 128 byte units ? writes data in 2-byte units ? 16384 8 bits ? ram ? 2048 9 bits ? bus cycle time ? 83.3ns (when cf=12mhz) note: the bus cycle time here refers to the rom read speed. ordering number : ena1835 cmos ic 16k-byte from and 2048-byte ram integrated 8-bit 1-chip microcontroller with usb-host controller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC87F1L16A no.a1835-2/24 ? minimum instruction cycle time (tcyc) ? 250ns (when cf=12mhz) ? ports ? i/o ports ports whose i/o direction can be designated in 1-bit units 26 (p10 to p17, p20 to p25, p30 to p34, p70 to p73, pwm0, pwm1, xt2) ports whose i/o direction can be designated in 4-bit units 8 (p00 to p07) ? usb ports 2 (uhad+, uhad-, uhbd+, uhbd-) ? dedicated oscillator ports 2 (cf1, cf2) ? input-only port (also used for oscillation) 1 (xt1) ? reset pins 1 ( res ) ? power supply pins 6 (v ss 1 to 3, v dd 1 to 3) ? timers ? timer 0: 16-bit timer/counter with 2 capture registers. mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with two 16-bit capture registers) mode 3: 16-bit counter (with two 16-bit capture registers) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescal er (with toggle out puts) + 8-bit timer/ counter with an 8-bit pres caler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as a pwm output) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes ? sio ? sio0: synchronous serial interface 1) lsb first/msb first mode selectable 2) transfer clock cycle: 4/3 to 512/3 tcyc 3) automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units) (suspension and resumption of data transmission possible in 1 byte units) ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? full duplex uart 1) data length: 7/8/9 bits selectable 2) stop bits: 1 bit (2 bits in continuous transmission mode) 3) baud rate: 16/3 to 8192/3 tcyc LC87F1L16A no.a1835-3/24 ? ad converter: 12 bits 12 channels ? pwm: multifrequency 12-bit pwm 2 channels ? usb interface (host control function) 2 channels 1) compliant with full-speed (12m bps) specifications 2) supports 4 transfer types (control transfer, bulk tr ansfer, interrupt transfer, and isochronous transfer). ? watchdog timer ? watchdog timer using external rc circuitry ? interrupt and reset signals selectable ? clock output function 1) can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as the system clock. 2) can output the source oscillation clock for the subclock. ? interrupts ? 39 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4/uhc-a bus active/uhc-b bus active 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h/int6/uhc-a device connected/uhc-a disconnected/uhc-a resume 6 0002bh h or l t1l/t1h/int7/uhc-b device connected/uhc-b disconnected/uhc-b resume 7 00033h h or l sio0/uart1 receive complete 8 0003bh h or l sio1/uart1 buffer empty/uart1 transmit complete 9 00043h h or l adc/t6/t7/uhc-ack/uhc-nak/uhc error/uhc stall 10 0004bh h or l port 0/pwm0/pwm1/t4/t5/uhc-sof ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 1024 levels maximum (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation and pll circuits ? rc oscillation circuit (internal): for system clock ? cf oscillation circuit: for system clock ? crystal oscillation circuit: for system clock, time-of-day clock ? pll circuit (internal): for usb interface (see fig.5) LC87F1L16A no.a1835-4/24 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting the hold mode. (1) setting the reset pin to the lower level (2) system resetting by watchdog timer (3) occurrence of an interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the pll base clock generator, cf, rc and cr ystal oscillators automatically stop operation. 2) there are five ways of resetting the hold mode. (1) setting the reset pin to the lower level (2) system resetting by watchdog timer (3) having an interrupt source established at either int0, int1, int2, int4 or int5 * int0 and int1 hold mode reset is available only when level detection is set. (4) having an interrupt source established at port 0 (5) having an bus active interrupt source established in the usb host controll circuit ? x'tal hold mode: suspends instruction execution and the opera tion of the peripheral circu its except the base timer. 1) the pll base clock generator, cf and rc oscillator automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are six ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) system resetting by watchdog timer (3) having an interrupt source established at either int0, int1, int2, int4 or int5 * int0 and int1 hold mode reset is available only when level detection is set. (4) having an interrupt source established at port 0 (5) having an interrupt source established in the base timer circuit (6) having an bus active interrupt source established in the usb host controll circuit ? package form ? sqfp48 (7 7): lead-/halogen-free type ? development tools ? on-chip debugger: tcb87 type-b + LC87F1L16A or tcb87 type-c (three wire cable) + LC87F1L16A ? flash rom programming boards package programming boards sqfp48(7 7) w87f55256sq ? flash programmer maker model supported version device flash support group, inc. (fsg) single programmer af9709/af9709b/af9709c (including ando electric co., ltd. models) rev 03.18c or later LC87F1L16A af9101/af9103 (main unit) (fsg models) flash support group, inc. (fsg) + sanyo (note 1) onboard single/gang programmer sib87(inter face driver) (sanyo model) (note 2) LC87F1L16A single/gang programmer skk/skk typeb (sanyofws) sanyo onboard single/gang programmer skk-dbg typeb (sanyofws) application version 1.04 or later chip data version 2.21 or later lc87f1l16 for information about af-series: flash support group, inc. tel: +81-53-459-1050 e-mail: sales@j-fsg.co.jp note1: on-board-programmer from fsg (af9101/af9103) and serial interface driver from sanyo (sib87) together can give a pc-less, standalone on-board-programming capabilities. note2: it needs a special programming devices and applications depending on the use of programming environment. please ask fsg or sanyo for the information. LC87F1L16A no.a1835-5/24 package dimensions unit : mm (typ) 3163b pin assignment sanyo : sqfp48(7 7) ?lead-/halogen-free type? sanyo : sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 uhad- uhad+ v dd 3 v ss 3 p34/ufilt p33 p32 p31/urx1 p30/utx1 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in 24 23 22 21 20 19 18 17 16 15 14 13 p03/an3/dbgp1 p02/an2/dbgp0 p01/an1 p00/an0 v ss 2 v dd 2 pwm0 pwm1 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 37 38 39 40 41 42 43 44 45 46 47 48 LC87F1L16A top view uhbd+ uhbd- p25/int5 p24/int5/int7 p23/int4 p22/int4 p21/int4 p20/int4/int6 p07/an7/t7o p06/an6/t6o p05/an5/cko p04/an4/dbgp2 p73/int3/t0in res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 LC87F1L16A no.a1835-6/24 sqfp48 name sqfp48 name 1 p73/int3/t0in 25 p04/an4/dbgp2 2 res 26 p05/an5/cko 3 xt1/an10 27 p06/an6/t6o 4 xt2/an11 28 p07/an7/t7o 5 v ss 1 29 p20/int4/int6 6 cf1 30 p21/int4 7 cf2 31 p22/int4 8 v dd 1 32 p23/int4 9 p10/so0 33 p24/int5/int7 10 p11/si0/sb0 34 p25/int5 11 p12/sck0 35 uhbd- 12 p13/so1 36 uhbd+ 13 p14/si1/sb1 37 uhad- 14 p15/sck1 38 uhad+ 15 p16/t1pwml 39 v dd 3 16 p17/t1pwmh/buz 40 v ss 3 17 pwm1 41 p34/ufilt 18 pwm0 42 p33 19 v dd 2 43 p32 20 v ss 2 44 p31/urx1 21 p00/an0 45 p30/utx1 22 p01/an1 46 p70/int0/t0lcp/an8 23 p02/an2/dbgp0 47 p71/int1/t0hcp/an9 24 p03/an3/dbgp1 48 p72/int2/t0in LC87F1L16A no.a1835-7/24 system block diagram interrupt control from standby control clock generator cf x?tal rc ir pla pc bus interface port 0 port 1 acc b register c register alu psw rar ram stack pointer watchdog timer base timer timer 4 pwm1 int0 to int7 noise filter sio0 port 2 usb pll port 7 port 3 adc sio1 timer 0 timer 1 pwm0 timer 5 timer 6 timer 7 uart1 onchip debugger usb host LC87F1L16A no.a1835-8/24 pin description pin name i/o description option v ss 1,v ss 2, v ss 3 - - power supply no v dd 1, v dd 2 - + power supply no v dd 3 - usb reference voltage yes port 0 p00 to p07 i/o ? 8-bit i/o ports ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units. ? hold reset input ? port 0 interrupt input ? pin functions ad converter input ports: an0 to an7(p00 to p07) onchip debugger pins: dbgp0 to dbgp2(p02 to p04) p05: system clock output p06: timer 6 toggle output p07: timer 7 toggle output yes port 1 p10 to p17 i/o ? 8-bit i/o ports ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p10: sio0 data out put p14: sio1 data input/bus input/output p11: sio0 data input/bus input/out put p15: sio1 clock input/output p12: sio0 clock input/output p16: timer 1 pwml output p13: sio1 data out put p17: timer 1 pwmh output/beeper output yes port 2 ? 6-bit i/o ports ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p20 to p23: int4 input/hold reset input/timer 1 event in put/timer 0l capture input/ timer 0h capture input p24 to p27: int5 input/hold reset input/timer 1 event in put/timer 0l capture input/ timer 0h capture input p20: int6 input/timer 0l capture 1 input p24: int7 input/timer 0h capture 1 input interrupt acknowledge types rising falling rising & falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable int6 enable enable enable disable disable int7 enable enable enable disable disable p20 to p25 i/o yes port 3 p30 to p34 i/o ? 5-bit i/o ports ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p30: uart1 transmit p31: uart1 receive p34: usb interface pll filter pin (see fig. 5.) yes continued on next page. LC87F1L16A no.a1835-9/24 continued from preceding page. pin name i/o description option port 7 ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p70: int0 input/hold reset input/time r 0l capture input/watchdog timer output p71: int1 input/hold reset i nput/timer 0h capture input p72: int2 input/hold reset input/timer 0 event input/timer 0l capture input/ high speed clock counter input p73: int3 input (input with noise filter) /timer 0 event input/timer 0h capture input ad converter input ports: an8(p70), an9(p71) interrupt acknowledge types rising falling rising & falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable p70 to p73 i/o no pwm0 pwm1 i/o pwm0, pwm1 output port general-purpose input port no uhad- uhad+ i/o usb-a port data i/o pin/general-purpose i/o port no uhbd- uhbd+ i/o usb-b port data i/o pin/general-purpose i/o port no res input reset pin no xt1 input ? 32.768khz crystal oscillator input ? pin functions general-purpose input port ad converter input ports: an10 must be connected to v dd 1 when not to be used. no xt2 i/o ? 32.768khz crystal oscillator output ? pin functions general-purpose i/o ad converter input port: an11 must be set for oscillation and kept open if not to be used. no cf1 input ceramic/crystal resonator input no cf2 output ceramic/crystal resonator output no LC87F1L16A no.a1835-10/24 on-chip debugger pin connection requirements for the treatment of the on-chip debugger pins, refer to the separately available documents entitled ?rd87 on-chip debugger installation manual? port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 1 bit 2 nch-open drain no 1 cmos programmable p10 to p17 p20 to p25 p30 to p34 1 bit 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable pwm0, pwm1 - no cmos no uhad+, uhad- uhbd+, uhbd- - no cmos no xt1 - no input only no xt2 - no 32.768khz crystal resonator output (n channel open drain when in general-purpose output mode) no note 1: programmable pull-up resistors for port 0 are controlled in 4 bit units (p00 to 03, p04 to 07). user option table option name option type mask version *1 flash version option selected in units of option selection cmos p00 to p07 enable enable 1 bit nch-open drain cmos p10 to p17 enable enable 1 bit nch-open drain cmos p20 to p25 enable enable 1 bit nch-open drain cmos port output form p30 to p34 enable enable 1 bit nch-open drain 00000h program start address - *2 enable - 03e00h use usb regulator enable enable - nonuse use usb regulator (at hold mode) enable enable - nonuse use usb regulator usb regulator (at halt mode) enable enable - nonuse enable main clock 8mhz selection - enable enable - disable *1: mask option selection ? no change possible after mask is completed. *2: program start address of the mask version is 00000h. LC87F1L16A no.a1835-11/24 usb reference power option when a voltage 4.5 to 5.5v is supplied to v dd 1 and the internal usb reference voltage circuit is activated, the reference voltage for usb port output is generated. the ac tive/inactive state of the reference voltage circuit can be switched by option select. the procedure for marking the option selection is described below. (1) (2) (3) (4) usb regulator use use use nonuse usb regulator at hold mode use nonuse nonuse nonuse option settings usb regulator at halt mode use nonuse use nonuse normal mode active active active inactive hold mode active inactive inactive inactive reference voltage circuit state halt mode active inactive active inactive ? when the usb reference voltage circuit is made inactive, th e level of the reference voltage for usb port output is equal to v dd 1. ? selection (2) or (3) can be used to set the reference voltage circuit inactive in hold or halt mode. ? when the reference voltage circuit is activated, the current drain increases by approximately 100 a compared with when the reference voltage circuit is inactive. example 1: v dd 1=v dd 2=3.3v ? inactivating the reference voltage circuit (selection (4)). ? connecting v dd 3 to v dd 1 and v dd 2. example 2: v dd 1=v dd 2=5.0v ? activating the reference volta ge circuit (selection (1)). ? isolating v dd 3 from v dd 1 and v dd 2, and connecting capacitor between v dd 3 and v ss . note: do not apply the voltage of more than 3.6v to uhad+, uhad-, uhbd+ and uhbd- when the reference voltage circuit is active. v ss 1 v ss 2v ss 3 v dd 1 v dd 2 v dd 3 power supply 3.3v lsi uhad+ /uhbd+ uhad- / uhbd- ufilt 15k to usb connector 33 5pf 0 2.2 2.2 to usb connector 33 5pf 2.2 LC87F1L16A no.a1835-12/24 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1= v dd 2= v dd 3 -0.3 +6.5 input voltage v i (1) xt1, cf1, res -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2, 3, 7 pwm0, pwm1 xt2 -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2 ? when cmos output type is selected ? per 1 applicable pin -10 ioph(2) pwm0, pwm1 per 1 applicable pin -20 peak output current ioph(3) port 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -5 iomh(1) ports 0, 1, 2 ? when cmos output type is selected ? per 1 applicable pin -7.5 iomh(2) pwm0, pwm1 per 1 applicable pin -15 average output current (note 1-1) iomh(3) port 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -3 ioah(1) ports 0, 2 to tal current of all applicable pins -25 ioah(2) port 1 pwm0, pwm1 total current of all applicable pins -25 ioah(3) ports 0, 1, 2 pwm0, pwm1 total current of all applicable pins -45 ioah(4) port 3 p71 to p73 total current of all applicable pins -10 high level output current total output current ioah(5) uhad+, uhad- uhbd+, uhbd- total current of all applicable pins -50 iopl(1) p02 to p07 ports 1, 2 pwm0, pwm1 per 1 applicable pin 20 iopl(2) p00, p01 per 1 applicable pin 30 peak output current iopl(3) ports 3, 7 xt2 per 1 applicable pin 10 ioml(1) p02 to p07 ports 1, 2 pwm0, pwm1 per 1 applicable pin 15 ioml(2) p00, p01 per 1 applicable pin 20 average output current (note 1-1) ioml(3) ports 3, 7 xt2 per 1 applicable pin 7.5 ioal(1) ports 0, 2 total current of all applicable pins 45 ioal(2) port 1 pwm0, pwm1 total current of all applicable pins 45 ioal(3) ports 0, 1, 2 pwm0, pwm1 total current of all applicable pins 80 ioal(4) ports 3, 7 xt2 total current of all applicable pins 15 low level output current total output current ioal(5) uhad+, uhad- uhbd+, uhbd- total current of all applicable pins 50 ma allowable power dissipation pd max sqfp48(7 7) ta=-40 to +85 c 140 mw operating ambient temperature topr -40 +85 storage ambient temperature tstg -55 +125 c note 1-1: the average output current is an average of current values measured over 100ms intervals. LC87F1L16A no.a1835-13/24 allowable operating conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit 0.245 s tcyc 200 s 3.0 5.5 0.245 s tcyc 0.383 s usb circuit active 3.0 5.5 operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.490 s tcyc 200 s except in onboard programming mode 2.7 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode. 2.0 5.5 v ih (1) port 0, 1, 2, 3 p71 to p73 p70 port input/ interrupt side pwm0, pwm1 2.7 to 5.5 0.3v dd +0.7 v dd v ih (2) port 70 watchdog timer side 2.7 to 5.5 0.9v dd v dd high level input voltage v ih (3) xt1, xt2, cf1, res 2.7 to 5.5 0.75v dd v dd v il (1) 4.0 to 5.5 v ss 0.1v dd +0.4 v il (2) port 1, 2, 3 p71 to p73 p70 port input/ interrupt side 2.7 to 4.0 v ss 0.2v dd v il (3) 4.0 to 5.5 v ss 0.15v dd +0.4 v il (4) port 0 pwm0, pwm1 2.7 to 4.0 v ss 0.2v dd v il (5) port 70 watchdog timer side 2.7 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (6) xt1, xt2, cf1, res 2.7 to 5.5 v ss 0.25v dd v 3.0 to 5.5 0.245 200 usb circuit active 3.0 to 5.5 0.245 0.383 instruction cycle time (note 2-2) tcyc except for onboard programming mode 2.7 to 5.5 0.490 200 s ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 3.0 to 5.5 0.1 12 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 2.7 to 5.5 0.1 6 mhz fmcf cf1, cf2 when 12m hz ceramic oscillation see fig. 1. 3.0 to 5.5 12 fmrc internal rc oscillation 2.7 to 5.5 0.3 1.0 2.0 mhz oscillation frequency range (note 2-3) fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 2. 2.7 to 5.5 32.768 khz note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants. LC87F1L16A no.a1835-14/24 electrical characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.7 to 5.5 1 i ih (2) xt1, xt2 input port configuration v in =v dd 2.7 to 5.5 1 high level input current i ih (3) cf1 v in =v dd 2.7 to 5.5 15 i il (1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.7 to 5.5 -1 i il (2) xt1, xt2 input port configuration v in =v ss 2.7 to 5.5 -1 low level input current i il (3) cf1 v in =v ss 2.7 to 5.5 -15 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ports 0, 1, 2, 3 p71 to p73 i oh =-0.2ma 2.7 to 5.5 v dd -0.4 v oh (4) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (5) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (6) pwm0, wm1 p05 (cko when using system clock output function) i oh =-1ma 2.7 to 5.5 v dd -0.4 v ol (1) i ol =30ma 4.5 to 5.5 1.5 v ol (2) i ol =5ma 3.0 to 5.5 0.4 v ol (3) p00, p01 i ol =2.5ma 2.7 to 5.5 0.4 v ol (4) i ol =10ma 4.5 to 5.5 1.5 v ol (5) i ol =1.6ma 3.0 to 5.5 0.4 v ol (6) ports 0, 1, 2 pwm0, pwm1 xt2 i ol =1ma 2.7 to 5.5 0.4 v ol (7) i ol =1.6ma 3.0 to 5.5 0.4 low level output voltage v ol (8) ports 3, 7 i ol =1ma 2.7 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 pull-up resistance rpu(2) ports 0, 1, 2, 3 port 7 v oh =0.9v dd 2.7 to 5.5 18 50 150 k hysteresis voltage vhys res port 1, 2, 3, 7 2.7 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.7 to 5.5 10 pf LC87F1L16A no.a1835-15/24 serial i/o characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 8. 1 tsckha(1a) ? continuous data transmission/ reception mode ? usb not used at the same time. ? see fig. 8. ? (note 4-1-2) 4 input clock high level pulse width tsckha(1b) sck0(p12) ? continuous data transmission/ reception mode ? usb used at the same time. ? see fig. 8. ? (note 4-1-2) 2.7 to 5.5 7 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? when cmos output type is selected ? see fig. 8. 1/2 tsck tsckha(2a) ? continuous data transmission/ reception mode ? usb not used at the same time. ? when cmos output type is selected ? see fig. 8. tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc serial clock output clock high level pulse width tsckha(2b) sck0(p12) ? continuous data transmission/ reception mode ? usb used at the same time. ? when cmos output type is selected. ? see fig. 8. 2.7 to 5.5 tsckh(2) +2tcyc tsckh(2) +(19/3) tcyc tcyc data setup time tsdi(1) 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 8. 2.7 to 5.5 0.03 tdd0(1) ? continuous data transmission/ reception mode ? (note 4-1-3) (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11) (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-1-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions. note 4-1-2: in an application where the serial clock input is to be used in the continuous data transfer mode, the time from si0run being set when serial clock is high to th e falling edge of the first serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 8. LC87F1L16A no.a1835-16/24 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig. 8. 2.7 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? when cmos output type is selected ? see fig. 8. 2.7 to 5.5 1/2 tsck data setup time tsdi(2) 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 8. 2.7 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 8. 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. ma rgins must be allowed according to the actual operating conditions. pulse input conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tp1h(1) tp1l(1) int0(p70), int1(p71), int2(p72), int4(p20 to p23), int5(p24 to p25), int6(p20), int7(p24) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are nabled. 2.7 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 256 tcyc high/low level pulse width tpil(5) res resetting is enabled. 2.7 to 5.5 200 s LC87F1L16A no.a1835-17/24 ad converter characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v <12-bits ad converter mode> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 12 bit absolute accuracy et (note 6-1) 3.0 to 5.5 16 lsb 4.5 to 5.5 32 115 conversion time tcad see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 64 115 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p00) to an7(p07), an8(p70), an9(p71), an10(xt1), an11(xt2) vain=v ss 3.0 to 5.5 -1 a <8-bits ad converter mode> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 20 90 conversion time tcad see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 40 90 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p00) to an7(p07), an8(p70), an9(p71), an10(xt1), an11(xt2) vain=v ss 3.0 to 5.5 -1 a conversion time calculation formulas : 12-bits ad converter mode : tcad (conversion time) = ((52/(ad division ratio))+2) (1/3) tcyc 8-bits ad converter mode : tcad (conversion time) = ((32/(ad division ratio))+2) (1/3) tcyc LC87F1L16A no.a1835-18/24 consumption current characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddop(1) 4.5 to 5.5 7.8 15 iddop(2) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ratio 3.0 to 3.6 4.6 8.4 iddop(3) 4.5 to 5.5 14 25 iddop(4) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode active ? internal rc oscillation stopped ? usb circuit active ? 1/1 frequency division ratio 3.0 to 3.6 7.1 14 iddop(5) 4.5 to 5.5 5.2 8.7 iddop(6) 3.0 to 3.6 3.4 5.6 iddop(7) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 2.8 4.6 iddop(8) 4.5 to 5.5 0.63 2.3 iddop(9) 3.0 to 3.6 0.37 1.3 iddop(10) ? fmcf=0hz (oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation. ? 1/2 frequency division ratio 2.7 to 3.0 0.32 1.0 ma iddop(11) 4.5 to 5.5 43 123 iddop(12) 3.0 to 3.6 17 52 normal mode consumption current (note 7-1) iddop(13) ? fmcf=0hz (oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to crystal oscillation. (32.768khz) ? internal rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 13 38 a iddhalt(1) 4.5 to 5.5 3.3 5.9 iddhalt(2) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ratio 3.0 to 3.6 1.7 3.1 iddhalt(3) 4.5 to 5.5 9.2 17 iddhalt(4) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode active ? internal rc oscillation stopped ? usb circuit active ? 1/1 frequency division ratio 3.0 to 3.6 4.3 8.3 iddhalt(5) 4.5 to 5.5 2.2 4.0 iddhalt(6) 3.0 to 3.6 1.1 2.0 iddhalt(7) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 0.88 1.5 iddhalt(8) 4.5 to 5.5 0.36 1.3 iddhalt(9) 3.0 to 3.6 0.18 0.62 halt mode consumption current (note7-1) iddhalt(10) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=0hz (oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation. ? 1/2 frequency division ratio 2.7 to 3.0 0.14 0.45 ma note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page. LC87F1L16A no.a1835-19/24 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddhalt(11) 4.5 to 5.5 31 99 iddhalt(12) 3.0 to 3.6 8.2 36 halt mode consumption current (note 7-1) iddhalt(13) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=0mhz (oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to crystal oscillation. (32.768khz) ? internal rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 5.5 25 iddhold(1) 4.5 to 5.5 0.10 24 iddhold(2) 3.0 to 3.6 0.04 13 hold mode consumption current iddhold(3) ? hold mode ? cf1=v dd or open (external clock mode) 2.7 to 3.0 0.03 11 iddhold(4) 4.5 to 5.5 28 92 iddhold(5) 3.0 to 3.6 6.6 32 timer hold mode consumption current iddhold(6) v dd 1 ? timer hold mode ? cf1=v dd or open (external clock mode) ? fsx?tal=32.768khz crystal oscillation mode 2.7 to 3.0 4.1 22 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors usb characteristics and timing at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol conditions min typ max unit high level output v oh(usb) ? 15k ? 5% to gnd 2.8 3.6 v low level output v ol(usb) ? 1.5k ? 5% to 3.6v 0.0 0.3 v output signal crossover voltage v crs 1.3 2.0 v differential input sensitivity v di ? ? (uhad+)-(uhad-) ? ? ? (uhbd+)-(uhbd-) ? 0.2 v differential input common mode range v cm 0.8 2.5 v high level input v ih(usb) 2.0 3.6 v low level input v il(usb) 0.0 0.8 v usb data rise time t r ? r s =33 , c l =50pf 4 20 ns usb data fall time t f ? r s =33 , c l =50pf 4 20 ns f-rom programming characteristics at ta = +10c to +55c, v ss 1 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 ma tfw(1) ? erase operation 20 30 ms programming time tfw(2) ? write operation 3.0 to 5.5 40 60 s LC87F1L16A no.a1835-20/24 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 shows the characteristics of a oscillati on circuit when usb host function is not used. if usb host function is to be used, it is absolutely recomme nded to use an oscillator that satisfies the precision and stability according to the usb standards. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz murata cstce12m0gh5l**-r0 (33) (33) 470 3.0 to 5.5 0.1 0.5 c1 and c2 integrated smd type the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized in the following cases (see figure 4): ? till the oscillation gets stabilized after v dd goes above the operating voltage lower limit. ? till the oscillation gets stabilized after the instruction fo r starting the main clock oscillation circuit is executed ? till the oscillation gets stabilized after the hold mode is reset. ? till the oscillation gets stabilized after the x'tal hold mode is reset with cfstop (ocr register, bit 0) set to 0 characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem clock oscillator circuit with a crystal oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 18 18 open 560k 2.7 to 5.5 1.1 3.0 applicable cl value=12.5pf smd type the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized in the following cases (see figure 4): ? till the oscillation gets stabilized after the instruction fo r starting the subclock oscillation circuit is executed ? till the oscillation gets stabilized after the hold mode is reset with extosc (ocr register, bit 6) set to 1 note: the components that are in volved in oscillation should be placed as close to the ic an d to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 crystal oscillator circuit rf rd2 xt1 xt2 c4 x?tal c3 rd1 cf1 cf2 c2 cf c1 LC87F1L16A no.a1835-21/24 figure 3 ac timing measurement point reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization time 0.5v dd internal rc oscillation cf1,cf2 xt1, xt2 operating mode hold reset signal hold reset signal valid tmscf tmsx?tal hold halt power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd operating v dd lower limit gnd LC87F1L16A no.a1835-22/24 figure 5 external filter circuit for th e internal usb-dedicated pll circuit figure 6 usb port peripheral circuit figure 7 reset circuit when using the internal pll circuit to generate the 48mhz clock for usb, it is necessary to connect a filter circuit such to as that shown the left to the p34/ufilt pin. rd 0k cd 2.2 uhd- uhd+ 5pf 33 15k 15k it?s necessary to adjust the circuit constant of the usb port peripheral circuit for each mounting board. c res v dd r res res note: determine the value of c res and r res so that the reset signal is present for a period of 200 s after the supply voltage goes beyond the lower limit of the ic's operating voltage. LC87F1L16A no.a1835-23/24 figure 8 serial input/output waveform figure 9 pulse input timing signal waveform figure 10 usb data signal timing and voltage level tpil tpih data ram transfer period (sio0 only) data ram transfer period (sio0 only) di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo t r t r d+ d- 10% 10% 90% 90% v oh v crs v ol LC87F1L16A no.a1835-24/24 ps this catalog provides information as of september, 2010. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. |
Price & Availability of LC87F1L16A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |